All about a Verilog V200x parser project hosted at SourceForge:

Wednesday, March 25, 2009

Unscheduled interruption (but a good one)

I have been adding a few fixes to the grammar and infrastructure: adding a symbol table and Simple Streaming Interface (SSI, as I call it): a file persistance mechanism. Hopefully, I'll have these posted next week, in a very alpha-ish state.

On the interrupt front: during my day job, I do a lot with synthesis and timing/design closure for large ASICs. I have been looking a lot at design/RTL and netlist quality (QOR) and to the latter: do a lot of manipulation/querying in either the synthesis tool or static timing analyzer, since both those have excellent (Tcl-based) UIs for such.

However, since those tools/licenses are very few and very $$$, it seemed natural to just strip down the v2kparse stuff for netlist-only type stuff. I had done an earlier (C++) type project at this sourceforge project and decided to shift gears a bit. So, I am in the process of revamping that project to use Java and Ruby: let's all say it together: JRuby!

At this point, I have the (netlist) and parser infrastructure completed in Antlr and Java, and have added a JRuby layer around it. For example: to iterate over a full (hierarchical) module/netlist to find and print (inefficient) instances of sequential cells with constant clocks and/or constant async set/reset pins, you simply:

#Find important reg pins tied to 0
msg = ": pin tied 0"
top_module.foreach_on_const_net(0) do |conns, val, inst_name|
conns.each do |conn|
if conn.isPin
pin =
Message.warn(pin.get_name(inst_name)+msg) if pin.get_name =~ /\/([CS]DN|CP)$/

Pretty cool!

Anyway, I want to flush through and post my updates to sourceforce and then update v2kparse shortly.

Stay tuned.