All about a Verilog V200x parser project hosted at SourceForge:

Monday, June 23, 2008

First pass uploaded to sourceforce

I finished the 1st pass of the ANTLR 2.7.7 based v2k parser and lexer and uploaded to sourceforge.

The lexer includes a Verilog preprocessor which handles:
  • `define,`undef
  • `include
  • `ifdef,`ifndef,`else,`endif
  • `timescale

Once you download, at the toplevel directory there is a runParser script which invokes java using the precompiled .jar files released under dist/.

Just type

> runParser

to see the usage.

I was compelled to use ANTLR 2.7.7 since the token stream mechanism does not try to slurp in the whole source file, an issue which I encountered with the more recent ANTLR 3.0.

While Verilog source files are not generally large, netlist files can be humungous, and one can quickly run out of memory by "slurping in the whole tamale."

Anyway, I've communicated the large file slurp file to the author of ANTLR and he'll be working out a solution in future releases.

(If you think large verilog netlists are problematic to slurp; think aout a SPEF file --- where I first encoutered the problem using ANTLR 3.x. Anyway, back to 2.7.7 works fine, even for large SPEF files.)

Anyway, back to the v2kparser...

I've been testing it out on a lot of the RTL for a large SOC I'm working on now; and, so far so good. It has even helped me find "bad style RTL" in the sense that (defined) 'values were used within source files which never `included the file containing the `define. Now, there's looking at an order of analysis problem!

I always advocate using the software style for writing include files and using them too, as in:

//file to be included all over: file.vh
`ifndef _FILE_VH
`define _FILE_VH_
`define N 5
`define M (1 << `N)

and the file which wants to use

`include "file.vh"

Wednesday, June 18, 2008

Implement what your verify

I spend a lot of my working hours doing ASIC design related tasks, primarily on the implementation side.

Hence, I've run through gazillions of lines of Verilog code, for lint tools, synthesis, formal EC, clock domain crossings, on and on.

I have yet to find a consistent way to feed Verilog file lists, include directories, library paths --- all that dot-f stuff: *.v, +incdir+, -y, -v, usu. dumped into a simulator "as-is" --- well, the implementation tools do not take those verbatim, you have to spec Tcl list of files, search paths, define arguments; and, don't even try to do anything resembling -y and +libext+ type options.

I've seen environments where I really wonder whether an ASIC was built with the same design files it was actually simulated with. (I kid you not!)

So, having spent lots of hours mucking around with EDA tool development of various sorts: simulators, parsers, databases and alike, I decided to solve the problem of getting simulation file stuff, verbatim, into the implementation tools.


Well, lets first start with a real parser, so we can process synthesizable Verilog RTL, including the preprocessor. From there, the sky is the limit.

For real parser development, there is one really excellent tool: ANTLR. I've been doing all kinds of hobby and real parser development with ANTLR since it was Terence's PhD thesis back in the late 80's.

There's all kinds of excellent info about ANTLR at the website, and even a great book to boot.