All about a Verilog V200x parser project hosted at SourceForge:

Wednesday, June 18, 2008

Implement what your verify

I spend a lot of my working hours doing ASIC design related tasks, primarily on the implementation side.

Hence, I've run through gazillions of lines of Verilog code, for lint tools, synthesis, formal EC, clock domain crossings, on and on.

I have yet to find a consistent way to feed Verilog file lists, include directories, library paths --- all that dot-f stuff: *.v, +incdir+, -y, -v, usu. dumped into a simulator "as-is" --- well, the implementation tools do not take those verbatim, you have to spec Tcl list of files, search paths, define arguments; and, don't even try to do anything resembling -y and +libext+ type options.

I've seen environments where I really wonder whether an ASIC was built with the same design files it was actually simulated with. (I kid you not!)

So, having spent lots of hours mucking around with EDA tool development of various sorts: simulators, parsers, databases and alike, I decided to solve the problem of getting simulation file stuff, verbatim, into the implementation tools.


Well, lets first start with a real parser, so we can process synthesizable Verilog RTL, including the preprocessor. From there, the sky is the limit.

For real parser development, there is one really excellent tool: ANTLR. I've been doing all kinds of hobby and real parser development with ANTLR since it was Terence's PhD thesis back in the late 80's.

There's all kinds of excellent info about ANTLR at the website, and even a great book to boot.

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