All about a Verilog V200x parser project hosted at SourceForge:

Monday, June 23, 2008

First pass uploaded to sourceforce

I finished the 1st pass of the ANTLR 2.7.7 based v2k parser and lexer and uploaded to sourceforge.

The lexer includes a Verilog preprocessor which handles:
  • `define,`undef
  • `include
  • `ifdef,`ifndef,`else,`endif
  • `timescale

Once you download, at the toplevel directory there is a runParser script which invokes java using the precompiled .jar files released under dist/.

Just type

> runParser

to see the usage.

I was compelled to use ANTLR 2.7.7 since the token stream mechanism does not try to slurp in the whole source file, an issue which I encountered with the more recent ANTLR 3.0.

While Verilog source files are not generally large, netlist files can be humungous, and one can quickly run out of memory by "slurping in the whole tamale."

Anyway, I've communicated the large file slurp file to the author of ANTLR and he'll be working out a solution in future releases.

(If you think large verilog netlists are problematic to slurp; think aout a SPEF file --- where I first encoutered the problem using ANTLR 3.x. Anyway, back to 2.7.7 works fine, even for large SPEF files.)

Anyway, back to the v2kparser...

I've been testing it out on a lot of the RTL for a large SOC I'm working on now; and, so far so good. It has even helped me find "bad style RTL" in the sense that (defined) 'values were used within source files which never `included the file containing the `define. Now, there's looking at an order of analysis problem!

I always advocate using the software style for writing include files and using them too, as in:

//file to be included all over: file.vh
`ifndef _FILE_VH
`define _FILE_VH_
`define N 5
`define M (1 << `N)

and the file which wants to use

`include "file.vh"


Draft said...

Can you give an example to use this parser in real asic design.

I am an asic designer, and interested in language, but I lack compiler background to understand the parser, I just want to use it. I have no time to study the details of how a parser is implemented!

Can you help me, give me some instructions.


kpfalzer said...

At this point, there is no tangible output, other than validating input against the synthesizable subset of the verilog 2005 language.

i.e., it will parse the files and "do nothing"; else, emit warnings/errors for invalid input.

I will be uploading another version soon which is towards my first pass goal of generating some XML views which can be subsequently used for file list generation. (Sounds like overkill for a seemingly simple task, huh?!)

Anyway, I would be curious to know what you would like to do w/ it? Or thought you could do w/ it?

Arik said...

Hi Karl,

Currently I'am trying to build a parser in C++ using ANTLR. I need to have the parser to parse the verilog files and fetch the information about modules, procedural statements, continueous statements, inputs, outputs, etc. I have already generated the Lexer and Parser C++ files using the Verilog grammar file downloaded from ANTLR website. The generated C++ files added to my VS2008 project and successfully compiled it. However I'd like to know how can I fetch the above mentioned information from verilog files. Could you please give some advice ?


kpfalzer said...

Hi Arik,

You will need to add some actions to the grammar rules. You should peruse the antlr website or the book from:

From the actions, you usually construct a parse tree ( Then, you walk the parse tree to manipulate/transform, ... the (specific) grammar/language context you desire for the application.

If you download my latest v2kparse from sourceforce, you should look at Vlog.g file which contains the grammar and actions to build a minimal parse tree which retains information about modules and instances.

I happen to use Java for the tree construction and JRuby for the tree walk, etc. But, the process would be the same for any language.

I am in the process of building a full-blown parse tree off the same Vlog.g. I expect that to be done in a few weeks.

You should consider joining the v2kparse project at sourceforge!

Anonymous said...

Hi Kpfalzer

I am a C developer .. and i need to add a new verilog syntax which is : array of instances
" nor_gate n[5:0] (sr,t,q);"
this is an array of nor gate of size 6 (6 nor gates) connected to sr[6:0] and so on ...
i stuck at the point how to add the array of instance to the verilog tree using C functions after parsing using yacc ,, i could parse so no syntax error appear but still can't add c functions to add these instances to the tree ... can you help please