All about a Verilog V200x parser project hosted at SourceForge:

Wednesday, March 25, 2009

Unscheduled interruption (but a good one)

I have been adding a few fixes to the grammar and infrastructure: adding a symbol table and Simple Streaming Interface (SSI, as I call it): a file persistance mechanism. Hopefully, I'll have these posted next week, in a very alpha-ish state.

On the interrupt front: during my day job, I do a lot with synthesis and timing/design closure for large ASICs. I have been looking a lot at design/RTL and netlist quality (QOR) and to the latter: do a lot of manipulation/querying in either the synthesis tool or static timing analyzer, since both those have excellent (Tcl-based) UIs for such.

However, since those tools/licenses are very few and very $$$, it seemed natural to just strip down the v2kparse stuff for netlist-only type stuff. I had done an earlier (C++) type project at this sourceforge project and decided to shift gears a bit. So, I am in the process of revamping that project to use Java and Ruby: let's all say it together: JRuby!

At this point, I have the (netlist) and parser infrastructure completed in Antlr and Java, and have added a JRuby layer around it. For example: to iterate over a full (hierarchical) module/netlist to find and print (inefficient) instances of sequential cells with constant clocks and/or constant async set/reset pins, you simply:

#Find important reg pins tied to 0
msg = ": pin tied 0"
top_module.foreach_on_const_net(0) do |conns, val, inst_name|
conns.each do |conn|
if conn.isPin
pin =
Message.warn(pin.get_name(inst_name)+msg) if pin.get_name =~ /\/([CS]DN|CP)$/

Pretty cool!

Anyway, I want to flush through and post my updates to sourceforce and then update v2kparse shortly.

Stay tuned.


mostafa said...

Hi Kpfalzer

I am a C developer .. and i need to add a new verilog syntax which is : array of instances
" nor_gate n[5:0] (sr,t,q);"
this is an array of nor gate of size 6 (6 nor gates) connected to sr[6:0] and so on ...
i stuck at the point how to add the array of instance to the verilog tree using C functions after parsing using yacc ,, i could parse so no syntax error appear but still can't add c functions to add these instances to the tree ... can you help please

kpfalzer said...

The verilog genvar/generate syntax can be used to create array of instances, as in:

The verilog grammar for the v2kparse project is IEEE 1364-2005 (synthesis subset) compliant and uses ANTLR( for parser generation. If you want to add non-compliant verilog syntax, you will have to modify the ANTLR style syntax file, etc. When you download from, you can find the grammar file under
Then, regenerate the parse using ANTLR.

kpfalzer said...

The example of verilog generate:

module addergen1 (co, sum, a, b, ci);
parameter SIZE = 4;
output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;
wire [SIZE :0] c;
wire [SIZE-1:0] t [1:3];
genvar i;
assign c[0] = ci;
// Hierarchical gate instance names are:
// xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
// bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2
// and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3
// bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4
// or gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5
// Generated instances are connected with
// multidimensional nets t[1][3:0] t[2][3:0] t[3][3:0]
// (12 nets total)
for(i=0; i<SIZE; i=i+1) begin:bit
xor g1 ( t[1][i], a[i], b[i]);
xor g2 ( sum[i], t[1][i], c[i]);
and g3 ( t[2][i], a[i], b[i]);
and g4 ( t[3][i], t[1][i], c[i]);
or g5 ( c[i+1], t[2][i], t[3][i]);
assign co = c[SIZE];

max said...

Any idea on the feasibility of doing something like this :

Most verilog people know Perl, but not too many know Ruby yet.